HD64F2149 Datasheet, PDF (555/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Master receive operation
Set TRS = 0 in ICCR
Set WAIT = 1 in ICMR
Set ACKB = 0 in ICSR
Read ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Last receive ? ^Yes
No
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Read ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Last receive ? ^Yes
No
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Set WAIT = 0 in ICMR
Read ICDR
Clear IRIC in ICCR
Write BBSY = 0
and SCP = 0 in ICCR
End
[1] Select receive mode.
[2] Start receiving. The first read
is a dummy read. After reading
ICDR, please clear IRIC immediately.
[3] Wait for 1 byte to be received
(8th clock falling edge)
[4] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
[5] Wait for 1 byte to be received.
(9th clock rising edge)
[6] Read the receive data.
[7] Clear IRIC.
[8] Wait for the next data to be
received.
(8th clock falling edge)
[9] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
[10] Set ACKB = 1 so as to return no
acknowledge, or set TRS = 1 so as
not to issue extra clock.
[11] Clear IRIC to trigger the 9th clock
(to end the wait insertion)
[12] Wait for 1 byte to be received.
[13] Set WAIT = 0.
Read ICDR.
Clear IRIC.
(Note: After setting WAIT = 0, IRIC
should be cleared to 0.)
[14] Stop condition issuance.
Figure 16.15 Flowchart for Master Receive Mode (Example)
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