HD64F2149 Datasheet, PDF (154/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 5.7 shows a block diagram of the priority decision circuit.
I UI
ICR
Interrupt
source
Interrupt
acceptance control
and 3-level mask
control
Default priority
determination
Vector
number
Interrupt control modes
0 and 1
Figure 5.7 Block Diagram of Interrupt Control Operation
Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,
interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in
CCR, and ICR (control level).
Table 5.6 shows the interrupts selected in each interrupt control mode.
Table 5.6 Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bits
Interrupt Control Mode I
UI
Selected Interrupts
0
0
*
All interrupts (control level 1 has priority)
1
*
NMI and address break interrupt
1
0
*
All interrupts (control level 1 has priority)
1
0
NMI, address break and control level 1 interrupts
1
NMI and address break interrupt
Legend:
*: Don’t care
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