HD64F2149 Datasheet, PDF (373/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.2.5 Timer Control/Status Register (TCSR)
TCSR0
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ADTE
0
R/W
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
TCSR1
Bit
7
6
5
4
CMFB CMFA OVF
—
Initial value
0
0
0
1
Read/Write R/(W)* R/(W)* R/(W)* —
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
TCSRX
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ICF
0
R/(W)*
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
TCSRY
Bit
Initial value
Read/Write
7
6
5
4
CMFB CMFA OVF ICIE
0
0
0
0
R/(W)* R/(W)* R/(W)* R/W
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
Note: * Only 0 can be written in bits 7 to 5, and in bit 4 in TCSRX, to clear these flags.
TCSR is an 8-bit register that indicates compare-match and overflow statuses (and input capture
status in TMRX only), and controls compare-match output.
TCSR0, TCSRX, and TCSRY are initialized to H'00, and TCSR1 is initialized to H'10, by a reset
and in hardware standby mode.
Bit 7—Compare-Match Flag B (CMFB): Status flag indicating whether the values of TCNT and
TCORB match.
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