HD64F2149 Datasheet, PDF (542/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Start condition generation
SCL
(Master output)
1
2
3
4
5
6
7
8
9
SDA
(Master output)
SDA
(Slave output)
[5]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W [7]
A
IRIC
1
2
Bit 7 Bit 6
Data 1
IRTR
ICDR
Precaution:
Data set timing to
ICDR
Incorrect operation
(ICDR writing
prohibited)
Address + R/W
Normal
operation
User processing [4] Write 1 to BBSY
and 0 to SCP
(start condition
issuance)
[6] ICDR write
[6] IRIC clear
Data 1
[9] ICDR write
[9] IRIC clear
Figure 16.7 Example of Master Transmit Mode Operating Timing (MLS = WAIT = 0)
16.3.3 Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits data.
The receive procedure and operations by which data is sequentially received in synchronization
with ICDR read operations, are described below.
[1] Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the
WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting).
[2] When ICDR is read (dummy data read), reception is started and the receive clock is output,
and data is received, in synchronization with the internal clock. To indicate the wait, clear the
IRIC flag to 0.
Reading from ICDR and clearing of the IRIC flag must be executed continuously so that no
interrupt is inserted.
If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is
cleared, the end of transfer cannot be identified.
[3] The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this
point, if the IEIC bit of ICCR is set to 1, an interrupt request is generated to the CPU.
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