HD64F2149 Datasheet, PDF (607/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Section 18B Host Interface
LPC Interface (LPC)
18B.1 Overview
The H8S/2169 or H8S/2149 has an on-chip host interface (HIF) that can be connected to the ISA
bus (X-BUS) widely used as the internal bus in personal computers. In addition, the H8S/2169 or
H8S/2149 has an on-chip LPC interface, a new host interface replacing the ISA bus. In the
following text, these two host interfaces (HIFs) are referred to as XBS and LPC, respectively.
The HIF:LPC performs serial transfer of cycle type, address, and data, synchronized with the 33
MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests.
Various kinds of cycle are available for the LPC interface, but the chip’s HIF:LPC supports only
I/O read cycle and I/O write cycle transfers.
The HIF:LPC consists of three register sets comprising data and status registers, plus a control
register, fast A20 gate logic, and a host interrupt request circuit. It is also provided with power-
down functions that can control the PCI clock and shut down the host interface.
The HIF:LPC ia available only in single-chip mode.
18B.1.1 Features
The features of the HIF:LPC are summarized below.
• Supports LPC interface I/O read cycles and I/O write cycles
 Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
 Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
• Has three register sets comprising data and status registers
 The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
 Channels 1 and 2 have fixed I/O addresses of H'60/H'64 and H'62/H'66, respectively,
enabling the same functions to be implemented as on HIF:XBS channels 1 and 2.
 A fast A20 gate function is also provided.
 The I/O address can be set for channel 3. Sixteen two-way register bytes can be
manipulated in addition to the basic register set.
• Supports SERIRQ
 Host interrupt requests are transferred serially on a single signal line (SERIRQ).
 On channel 1, HIRQ1 and HIRQ12 can be generated.
 On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
573