HD64F2149 Datasheet, PDF (18/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

2.8.6 Power-Down State................................................................................................ 68
2.9 Basic Timing...................................................................................................................... 69
2.9.1 Overview .............................................................................................................. 69
2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 69
2.9.3 On-Chip Supporting Module Access Timing (Internal I/O Register 1 and 2) ..... 71
2.9.4 On-Chip Supporting Module Access Timing (Interna I/O Register 3) ................ 73
2.9.5 External Address Space Access Timing............................................................... 74
2.10 Usage Note ........................................................................................................................ 74
2.10.1 TAS Instruction .................................................................................................... 74
2.10.2 STM/LDM Instruction.......................................................................................... 74
Section 3 MCU Operating Modes ................................................................................ 75
3.1 Overview............................................................................................................................ 75
3.1.1 Operating Mode Selection.................................................................................... 75
3.1.2 Register Configuration ......................................................................................... 76
3.2 Register Descriptions......................................................................................................... 76
3.2.1 Mode Control Register (MDCR).......................................................................... 76
3.2.2 System Control Register (SYSCR) ...................................................................... 77
3.2.3 Bus Control Register (BCR) ................................................................................ 79
3.2.4 Serial Timer Control Register (STCR)................................................................. 80
3.3 Operating Mode Descriptions............................................................................................ 82
3.3.1 Mode 1.................................................................................................................. 82
3.3.2 Mode 2.................................................................................................................. 82
3.3.3 Mode 3.................................................................................................................. 82
3.4 Pin Functions in Each Operating Mode............................................................................. 83
3.5 Memory Map in Each Operating Mode............................................................................. 83
Section 4 Exception Handling........................................................................................ 87
4.1 Overview............................................................................................................................ 87
4.1.1 Exception Handling Types and Priority ............................................................... 87
4.1.2 Exception Handling Operation ............................................................................. 88
4.1.3 Exception Sources and Vector Table.................................................................... 88
4.2 Reset .................................................................................................................................. 90
4.2.1 Overview .............................................................................................................. 90
4.2.2 Reset Sequence..................................................................................................... 90
4.2.3 Interrupts after Reset ............................................................................................ 92
4.3 Interrupts............................................................................................................................ 93
4.4 Trap Instruction ................................................................................................................. 94
4.5 Stack Status after Exception Handling .............................................................................. 95
4.6 Notes on Use of the Stack.................................................................................................. 96
Section 5 Interrupt Controller ........................................................................................ 97
5.1 Overview............................................................................................................................ 97
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