HD64F2149 Datasheet, PDF (347/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 2
OEB
0
1
Description
Output compare B output is disabled
Output compare B output is enabled
(Initial value)
Bit 1—Output Level A (OLVLA): Selects the logic level to be output at the FTOA pin in
response to compare-match A (signal indicating a match between the FRC and OCRA values).
When the OCRAMS bit is 1, this bit is ignored.
Bit 1
OLVLA
0
1
Description
0 output at compare-match A
1 output at compare-match A
(Initial value)
Bit 0—Output Level B (OLVLB): Selects the logic level to be output at the FTOB pin in
response to compare-match B (signal indicating a match between the FRC and OCRB values).
Bit 0
OLVLB
0
1
Description
0 output at compare-match B
1 output at compare-match B
(Initial value)
11.2.10 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
7654321076543210
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13 bit is set to 1, FRT operation is stopped at the end of the bus cycle, and
module stop mode is entered. For details, see section 24.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
313