HD64F2149 Datasheet, PDF (893/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

ODR3—Output Data Register 3
ODR1—Output Data Register 1
ODR2—Output Data Register 2
H'FE31
H'FE39
H'FE3D
HIF (LPC)
HIF (LPC)
HIF (LPC)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
Bit 7
—
R/W
R
6
Bit 6
—
R/W
R
5
Bit 5
—
R/W
R
4
Bit 4
—
R/W
R
3
Bit 3
—
R/W
R
2
Bit 2
—
R/W
R
1
Bit 1
—
R/W
R
0
Bit 0
—
R/W
R
Read by host using I/O address in table below*
I/O address
Transfer
Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 ^cycle
Host register
selection
0000 0000 0110 0 0 0 0 I/O read ODR1 read
0000 0000 0110 0 0 1 0 I/O read ODR2 read
Note: * For information on ODR3 selection, see LPC Channel 3 Address
Register (LADR3).
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