HD64F2149 Datasheet, PDF (414/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 13.5 Examples of TCR and TCSR Settings
Register
TCR in TMR1
Bit(s) Abbreviation
7
CMIEB
6
CMIEA
5
OVIE
4 and 3 CCLR1, CCLR0
2 to 0 CKS2 to CKS0
TCSR in TMR1 3 to 0 OS3 to OS0
TCR in FRT
6
IEDGB
1 and 0 CKS1, CKS0
TCSR in FRT 0
CCLRA
Contents
0
0
0
11
101
0011
1001
0/1
01
0
Description
Interrupts due to compare-match
and overflow are disabled
TCNT is cleared by the rising edge
of the external reset signal (Inverse
of the IVI signal)
TCNT is incremented on the rising
edge of the external clock (IHI
signal)
Not changed by compare-match B;
output inverted by compare-match A
(toggle output): division by 512
or
when TCORB < TCORA, 1 output
on compare-match B, and 0 output
on compare-match A: division by
256
0: FRC value is transferred to ICRB
on falling edge of input capture input
B (IHI divided signal waveform)
1: FRC value is transferred to ICRB
on rising edge of input capture input
B (IHI divided signal waveform)
FRC is incremented on internal
clock: ø/8
FRC clearing is disabled
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