HD64F2149 Datasheet, PDF (308/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

9.2 Register Descriptions
9.2.1 PWM Register Select (PWSL)
Bit
7
6
5
PWCKE PWCKS —
Initial value
0
0
1
Read/Write
R/W
R/W
—
4
3
2
1
0
—
RS3 RS2 RS1 RS0
0
0
0
0
0
—
R/W R/W R/W R/W
PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the
PWM data register.
PWSL is initialized to H'20 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 and 6—PWM Clock Enable, PWM Clock Select (PWCKE, PWCKS): These bits,
together with bits PWCKA and PWCKB in PCSR, select the internal clock input to TCNT in the
PWM timer.
PWSL
Bit 7
Bit 6
PWCKE PWCKS
0
—
1
0
1
PCSR
Bit 2
Bit 1
PWCKB PWCKA
—
—
—
—
0
0
1
1
0
1
Description
Clock input is disabled
ø (system clock) is selected
ø/2 is selected
ø/4 is selected
ø/8 is selected
ø/16 is selected
(Initial value)
The PWM resolution, PWM conversion period, and carrier frequency depend on the selected
internal clock, and can be found from the following equations.
Resolution (minimum pulse width) = 1/internal clock frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
Thus, with a 10 MHz system clock (ø), the resolution, PWM conversion period, and carrier
frequency are as shown followings.
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