HD64F2149 Datasheet, PDF (349/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

ø
External
clock input pin
FRC input
clock
FRC
N
N+1
Figure 11.4 Increment Timing with External Clock Source
11.3.2 Output Compare Output Timing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or
OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the
timing of this operation for compare-match A.
ø
FRC
N
N+1
N
N+1
OCRA
N
Compare-match A
signal
OLVLA
N
Clear*
Output compare A
output pin FTOA
Note: * Vertical arrows ( ) indicate instructions executed by software.
Figure 11.5 Timing of Output Compare A Output
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