HD64F2149 Datasheet, PDF (650/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18B.4 Interrupt Sources
18B.4.1 IBF1, IBF2, IBF3, ERRI
The host interface has four interrupt requests for the slave processor: IBF1, IBF2, IBF3, and
ERRI. IBF1, IBF2, and IBF3 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and
TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC
reset, LPC shutdown, or transfer cycle abort. An interrupt request is enable by setting the
corresponding enable bit,
Table 18B.7 Receive Complete Interrupts and Error Interrupt
Interrupt
IBF1
IBF2
IBF3
ERRI
Description
Requested when IBFIE1 is set to 1 and IDR1 reception is completed
Requested when IBFIE2 is set to 1 and IDR2 reception is completed
Requested when IBFIE3 is set to 1 and IDR3 reception is completed, or when
TWRE and IBFIE3 are set to 1 and reception is completed up to TWR15
Requested when ERRIE is set to 1 and LRST, SDWN, or ABRT is set to 1
18B.4.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, HIRQ12
The host interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and
HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can
be requested from LPC channel 2 or 3.
There are two ways of clearing a host interrupt request.
When the IEDIR bit is cleared to 0 in SIRQCR0, host interrupt sources and LPC channels are all
linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read by the
host of ODR or TWR15 in the corresponding LPC channel, the corresponding host interrupt
enable bit is automatically cleared to 0, and the host interrupt request is cleared.
When the IEDIR bit is set to 1 in SIRQCR0, LPC channel 2 and 3 interrupt requests are dependent
only upon the host interrupt enable bits. The host interrupt enable bit is not cleared when OBF for
channel 2 or 3 is cleared. Therefore, SMIE2, SMIE3A and SMIE3B, IRQ6E2 and IRQ6E3,
IRQ9E2 and IRQ9E3, IRQ10E2 and IRQ10E3, and IRQ11E2 and IRQ11E3 lose their respective
functional differences. In order to clear a host interrupt request, it is necessary to clear the host
interrupt enable bit.
Table 18B.8 summarizes the methods of setting and clearing these bits, and figure 18B.8 shows
the processing flowchart.
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