HD64F2149 Datasheet, PDF (401/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bits 7 and 6—Input Synchronization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits
select the signal source of the IHI and IVI signals.
Bit 7
SIMOD1
0
1
Bit 6
SIMOD0
0
1
0
1
Description
Mode
IHI Signal
No signal (Initial value) HFBACKI input
S-on-G mode
CSYNCI input
Composite mode
HSYNCI input
Separate mode
HSYNCI input
IVI Signal
VFBACKI input
PDC input
PDC input
VSYNCI input
Bit 5—Synchronization Signal Connection Enable (SCONE): Selects the signal source of the
FRT FTI input and the TMR1 TMCI1/TMRI1 input.
Bit 5
Description
SCONE Mode
FTIA FTIB FTIC
FTID TMCI1 TMRI1
0
Normal connection (Initial value) FTIA FTIB FTIC
FTID TMCI1 TMRI1
input input input
input input input
1
Synchronization signal
connection mode
IVI
TMO1 VFBACKI IHI IHI
IVI
signal signal input
signal signal inverse
signal
Bit 4—Input Capture Start Bit (ICST): The TMRX external reset input (TMRIX) is connected
to the IHI signal. TMRX has input capture registers (TICR, TICRR, and TICRF). TICRR and
TICRF can measure the width of a short pulse by means of a single capture operation under the
control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after
the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
Bit 4
ICST
0
1
Description
The TICRR and TICRF input capture functions are stopped
(Initial value)
[Clearing condition]
When a rising edge followed by a falling edge is detected on TMRIX
The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
367