HD64F2149 Datasheet, PDF (591/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18A.2 Register Descriptions
18A.2.1 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
2
NMIEG
0
R/W
1
HIE
0
R/W
0
RAME
1
R/W
SYSCR is an 8-bit readable/writable register which controls the chip operations. Of the host
interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be accessed
when the HIE bit is set to 1. HICR2, IDR3, ODR3, STR3, IDR4, ODR4, and STR4 can be
accessed regardless of the setting of the HIE bit. The host interface CS2 and ECS2 pins are
controlled by the CS2E bit in SYSCR and the FGA20E bit in HICR. See section 3.2.2, System
Control Register (SYSCR), and section 5.2.1, System Control Register (SYSCR), for information
on other SYSCR bits. SYSCR is initialized to H'09 by a reset and in hardware standby mode.
Bit 7—CS2 Enable Bit (CS2E): Used together with the FGA20E bit in HICR to select the pin
that performs the CS2 pin function when the HI12E bit is set to 1.
SYSCR
Bit 7
CS2E
0
1
HICR
Bit 0
FGA20E
0
1
0
1
Description
CS2 pin function halted (CS2 fixed high internally)
CS2 pin function selected for P81/CS2 pin
CS2 pin function selected for P90/ECS2 pin
(Initial value)
Bit 1—Host Interface Enable Bit (HIE): Enables or disables CPU access to the host interface
registers, keyboard matrix interrupt mask register (KMIMR), keyboard matrix interrupt mask
register A (KMIMRA), and port 6 MOS pull-up control register (KMPCR). When enabled, the
host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2) can be accessed.
Bit 1
HIE
0
1
Description
HIF:XBS register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is
disabled
(Initial value)
HIF:XBS register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is
enabled
557