HD64F2149 Datasheet, PDF (749/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

24.1.1 Register Configuration
The power-down state is controlled by the SBYCR, LPWRCR, TCSR (WDT1), and MSTPCR
registers. Table 24.3 summarizes these registers.
Table 24.3 Power-Down State Registers
Name
Abbreviation R/W
Initial Value
Address*¹
Standby control register
SBYCR
R/W
H'00
H'FF84*²
Low-power control register
LPWRCR
R/W
H'00
H'FF85*²
Timer control/status register
(WDT1)
TCSR
R/W
H'00
H'FFEA
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86*²
MSTPCRL
R/W
H'FF
H'FF87*²
Notes: 1. Lower 16 bits of the address.
2. A CPU access to some of the control registers in the power-down state is controlled by
the FLSHE bit of the serial/timer control register (STCR).
24.2 Register Descriptions
24.2.1 Standby Control Register (SBYCR)
Bit
7
6
5
4
3
2
1
0
SSBY STS2 STS1 STS0
—
SCK2 SCK1 SCK0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Software Standby (SSBY): Determines the operating mode, in combination with other
control bits, when a power-down mode transition is made by executing a SLEEP instruction. The
SSBY setting is not changed by a mode transition due to an interrupt, etc.
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