HD64F2149 Datasheet, PDF (296/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

8.15.2 Register Configuration
Table 8.29 is a summary of the port E and port F registers.
Table 8.29 Port E and port F Registers
Name
Abbreviation R/W
Port E data direction register
PEDDR
W
Port E output data register
PEODR
R/W
Port E input data register
PEPIN
R
Port E Nch-OD control register PENOCR
R/W
Port F data direction register
PFDDR
W
Port F output data register
PFODR
R/W
Port F input data register
PFPIN
R
Port F Nch-OD control register PFNOCR
R/W
Notes: 1. Lower 16 bits of the address.
2. PEDDR has the same address as PEPIN.
3. PFDDR has the same address as PFPIN.
Initial Value
H'00
H'00
Undefined
H'00
H'00
H'00
Undefined
H'00
Address*¹
H'FE4A*²
H'FE48
H'FE4A*²
H'FE18
H'FE4B*³
H'FE49
H'FE4B*³
H'FE19
Port E and port F Data Direction Registers (PEDDR, PFDDR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PEDDR and PFDDR are 8-bit write-only registers, the individual bits of which select input or
output for the pins of port E and port F. PEDDR and PFDDR are at the same addresses as PEPIN
and PFPIN, respectively, and if read, will return the port E and port F pin states.
Setting a PEDDR or PFDDR bit to 1 makes the corresponding pin on port E or port F an output
pin, while clearing the bit to 0 makes the pin an input pin.
PEDDR and PFDDR are initialized to H'00 by a reset and in hardware standby mode. They retain
their prior states in software standby mode.
262