HD64F2149 Datasheet, PDF (270/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

When the ABW bit in WSCR is cleared to 0, pin P90 becomes a bus control output (LWR),
regardless of the input/output direction indicated by P90DDR. When the ABW bit is 1, pin P90
becomes an output port if P90DDR is set to 1, and an input port if P90DDR is cleared to 0.
• Modes 2 and 3 (EXPE = 0)
When the corresponding P9DDR bits are set to 1, pin P96 functions as the ø output pin and
pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the
corresponding pins become input ports.
Port 9 Data Register (P9DR)
Bit
7
6
5
P97DR P96DR P95DR
Initial value
0
—*
0
Read/Write R/W
R
R/W
Note: * Determined by the state of pin P96.
4
P94DR
0
R/W
3
P93DR
0
R/W
2
P92DR
0
R/W
1
P91DR
0
R/W
0
P90DR
0
R/W
P9DR is an 8-bit readable/writable register that stores output data for the port 9 pins (P97 to P90).
With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR
values are read directly, regardless of the actual pin states. If a port 9 read is performed while
P9DDR bits are cleared to 0, the pin states are read.
P9DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
8.10.3 Pin Functions
Port 9 pins also function as external interrupt input pins (IRQ0 to IRQ2), the A/D converter trigger
input pin (ADTRG), host interface (XBS) input pins (ECS2, CS1, IOW, IOR), the IIC0 I/O pin
(SDA0), the subclock input pin (EXCL), bus control signal I/O pins (AS/IOS, RD, HWR, LWR,
WAIT), and the system clock (ø) output pin. The pin functions differ between the mode 1, 2, and 3
(EXPE = 1) expanded modes and the mode 2 and 3 (EXPE = 0) single-chip modes. The port 9 pin
functions are shown in table 8.19.
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