HD64F2149 Datasheet, PDF (623/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
0
0
1
0
0
1
I/O Address
Bit 2 Bit 1
0
Bit 1
1
Bit 1
0
Bit 1
1
Bit 1
0
0
0
0
•
•
•
1
1
0
0
0
0
•
•
•
1
1
Bit 0
0
0
0
0
0
1
1
0
1
1
Transfer
Cycle
I/O write
I/O write
I/O read
I/O read
I/O write
I/O write
I/O read
I/O read
Host Register Selection
IDR3 write, C/D3 ← 0
IDR3 write, C/D3 ← 1
ODR3 read
STR3 read
TWR0MW write
TWR1 to TWR15 write
TWR0SW read
TWR1 to TWR15 read
LADR3L Bit 2—Reserved: This is a readable/writable reserved bit.
LADR3L Bit 0—Two-Way Register Enable (TWRE): Enables or disables two-way register
operation.
LADR3L
Bit 0
TWRE
0
1
Description
TWR operation is disabled
TWR-related I/O address match determination is halted
TWR operation is enabled
(Initial value)
18B.2.5 Input Data Registers (IDR1, IDR2, IDR3)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
Bit 7
—
R
W
6
Bit 6
—
R
W
5
Bit 5
—
R
W
4
Bit 4
—
R
W
3
Bit 3
—
R
W
2
Bit 2
—
R
W
1
Bit 1
—
R
W
0
Bit 0
—
R
W
589