HD64F2149 Datasheet, PDF (340/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running
timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit 1
OVIE
0
1
Description
Timer overflow interrupt request (FOVI) is disabled
Timer overflow interrupt request (FOVI) is enabled
(Initial value)
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
11.2.7 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)*
6
ICFB
0
R/(W)*
5
ICFC
0
R/(W)*
4
ICFD
0
R/(W)*
3
OCFA
0
R/(W)*
2
OCFB
0
R/(W)*
1
0
OVF CCLRA
0
0
R/(W)* R/W
Note: * Only 0 can be written in bits 7 to 1 to clear these flags.
TCSR is an 8-bit register used for counter clear selection and control of interrupt request signals.
TCSR is initialized to H'00 by a reset and in hardware standby mode.
Timing is described in section 11.3, Operation.
Bit 7—Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been
transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that
the old ICRA value has been moved into ICRC and the new FRC value has been transferred to
ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7
ICFA
0
1
Description
[Clearing condition]
(Initial value)
Read ICFA when ICFA = 1, then write 0 in ICFA
[Setting condition]
When an input capture signal causes the FRC value to be transferred to
ICRA
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