HD64F2149 Datasheet, PDF (554/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

520
Start
Initialize
Read BBSY in ICCR
No
BBSY = 0 ?
Yes
Set MST = 1 and
TRS = 1 in ICCR
Write BBSY = 1 and
SCP = 0 in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Read ACKB in ICSR
ACKB = 0 ?
No
Yes
No
Transmit mode ?
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Read ACKB in ICSR
No
End of transmission ?
or ACKB = 1 ?
Yes
Clear IRIC in ICCR
Write BBSY = 0
and SCP = 0 in ICCR
End
[1] Initialize
[2] Test the status of the SCL and SDA lines.
[3] Select master transmit mode.
[4] Start condition issuance
[5] Wait for a start condition
[6] Set transmit data for the first byte
(slave address + R/W).
(After writing ICDR, clear IRIC
immediately)
[7] Wait for 1 byte to be transmitted.
[8] Test the acknowledge bit,
transferred from slave device.
Master receive mode
[9] Set transmit data for the second and
subsequent bytes.
(After writing ICDR, clear IRIC immediately.)
[10] Wait for 1 byte to be transmitted.
[11] Test for end of transfer
[12] Stop condition issuance
Figure 16.14 Flowchart for Master Transmit Mode (Example)