HD64F2149 Datasheet, PDF (28/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

17.2.2 Keyboard Control Register L (KBCRL) .............................................................. 536
17.2.3 Keyboard Data Buffer Register (KBBR) ............................................................. 538
17.2.4 Module Stop Control Register (MSTPCR) .......................................................... 538
17.3 Operation ........................................................................................................................... 539
17.3.1 Receive Operation ................................................................................................ 539
17.3.2 Transmit Operation .............................................................................................. 541
17.3.3 Receive Abort....................................................................................................... 544
17.3.4 KCLKI and KDI Read Timing ............................................................................. 547
17.3.5 KCLKO and KDO Write Timing ......................................................................... 547
17.3.6 KBF Setting Timing and KCLK Control ............................................................. 548
17.3.7 Receive Timing .................................................................................................... 549
17.3.8 KCLK Fall Interrupt Operation............................................................................ 550
17.3.9 Usage Note ........................................................................................................... 551
Section 18A Host Interface
X-Bus Interface (XBS).............................................................................. 553
18A.1 Overview .......................................................................................................................... 553
18A.1.1 Features ............................................................................................................ 553
18A.1.2 Block Diagram.................................................................................................. 554
18A.1.3 Input and Output Pins....................................................................................... 555
18A.1.4 Register Configuration ..................................................................................... 556
18A.2 Register Descriptions........................................................................................................ 557
18A.2.1 System Control Register (SYSCR) .................................................................. 557
18A.2.2 System Control Register 2 (SYSCR2) ............................................................. 558
18A.2.3 Host Interface Control Register (HICR) .......................................................... 559
18A.2.4 Input Data Register (IDR) ................................................................................ 561
18A.2.5 Output Data Register (ODR)............................................................................ 561
18A.2.6 Status Register (STR) ....................................................................................... 562
18A.2.7 Module Stop Control Register (MSTPCR) ...................................................... 564
18A.3 Operation .......................................................................................................................... 564
18A.3.1 Host Interface Activation ................................................................................. 564
18A.3.2 Control States ................................................................................................... 566
18A.3.3 A20 Gate .......................................................................................................... 566
18A.3.4 Host Interface Pin Shutdown Function ............................................................ 568
18A.4 Interrupts .......................................................................................................................... 570
18A.4.1 IBF1, IBF2, IBF3, IBF4 ................................................................................... 570
18A.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ............................................ 570
18A.5 Usage Note ....................................................................................................................... 572
Section 18B Host Interface
LPC Interface (LPC).................................................................................. 573
18B.1 Overview .......................................................................................................................... 573
18B.1.1 Features ............................................................................................................ 573
xii