HD64F2149 Datasheet, PDF (416/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 13.6 Examples of TCR, TCSR, TCOR, and OCRDM Settings
Register
TCR in FRT
Bit(s)
4
Abbreviation
IEDGD
1 and 0 CKS1, CKS0
TCSR in FRT 0
TCOR in FRT 7
CCLRA
ICRDMS
OCRDM in FRT 7 to 0 OCRDM7 to 0
Contents Description
1
FRC value is transferred to ICRD on
the rising edge of input capture input
D (IHI signal)
01
FRC is incremented on internal clock:
ø/8
0
FRC clearing is disabled
1
ICRD is set to the operating mode in
which OCRDM is used
H'01 to H'FF Specifies the period during which
ICRD operation is masked
IHI signal
(without 2fH
modification)
IHI signal
(with 2fH
modification)
Mask interval
ICRD + OCRDM × 2
ICRD + OCRDM
FRC
ICRD
Figure 13.6 2fH Modification Timing Chart
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