HD64F2149 Datasheet, PDF (897/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SIRQCR0—SERIRQ Control Register 0
H'FE36
HIF (LPC)
Bit
7
Q/C
Initial value
0
Slave Read/Write R
Host Read/Write
—
6
5
4
3
2
1
0
— IEDIR SMIE3B SMIE3A SMIE2 IRQ12E1 IRQ1E1
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
—
—
—
—
—
—
—
HIRQ1 interrupt enable 1
0 HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled
[Clearing conditions]
• Writing 0 to IRQ1E1
• LPC hardware reset, LPC software reset
• Clearing OBF1 to 0
1 HIRQ1 interrupt request by setting OBF1 to 1 is enabled
[Setting condition]
• Writing 1 after reading IRQ1E1 = 0
HIRQ12 interrupt enable 1
0 HIRQ12 interrupt request by OBF1 and IRQ12E1 is disabled
[Clearing conditions]
• Writing 0 to IRQ12E1
• LPC hardware reset, LPC software reset
• Clearing OBF1 to 0
1 HIRQ12 interrupt request by setting OBF1 to 1 is enabled
[Setting condition]
• Writing 1 after reading IRQ12E1 = 0
SMI interrupt enable 2
0 SMI interrupt request by OBF2 and SMIE2 is disabled
[Clearing conditions]
• Writing 0 to SMIE2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
1 [When IEDIR = 0] SMI interrupt request by setting OBF2 to 1 is enabled
[When IEDIR = 1] SMI interrupt is requested
[Setting condition]
• Writing 1 after reading SMIE2 = 0
SMI interrupt enable 3A
0 SMI interrupt request by OBF3A and SMIE3A is disabled
[Clearing conditions]
• Writing 0 to SMIE3A
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
1 [When IEDIR = 0] SMI interrupt request by setting OBF3A to 1 is enabled
[When IEDIR = 1] SMI interrupt is requested
[Setting condition]
• Writing 1 after reading SMIE3A = 0
SMI interrupt enable 3B
Reserved
0 SMI interrupt request by OBF3B and SMIE3B is disabled
[Clearing conditions]
• Writing 0 to SMIE3B
• LPC hardware reset, LPC software reset
• Clearing OBF3B to 0 (when IEDIR = 0)
1 [When IEDIR = 0] SMI interrupt request by setting OBF3B to 1 is enabled
[When IEDIR = 1] SMI interrupt is requested
[Setting condition]
• Writing 1 after reading SMIE3B = 0
Interrupt enable direct mode
Quiet/continuous mode flag
0 Host interrupt is requested when host interrupt enable bit and corresponding OBF are both set to 1
1 Host interrupt is requested when host interrupt enable bit is set to 1
0 Continuous mode
[Clearing conditions]
• LPC hardware reset, LPC software reset
• Specification by SERIRQ transfer cycle stop frame
1 Quiet mode
[Setting condition]
• Specification by SERIRQ transfer cycle stop frame
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