HD64F2149 Datasheet, PDF (10/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

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Revision (See Manual for Details)
15.2.8 Bit Rate Register Note added
Table 15.3 BRR Settings for Various Bit Rates
φ = 12 MHz or more deleted
Table 15.4 BRR Settings for Various Bit Rates
φ = 16 MHz or more deleted
Table 15.5 Maximum Bit Rate for Each Frequency
φ = 12 MHz or more deleted
Table 15.6 Maximum Bit Rate with External Clock Input
φ = 12 MHz or more deleted
Table 15.7 Maximum Bit Rate with External Clock Input
φ = 12 MHz or more deleted
15.3.2 Operation in
Asynchronous Mode
Figure 15.8 Example of SCI Operation in Reception
Amended (Stop bit)
15.3.3 Multiprocessor
Figure 15.10 Sample Multiprocessor Serial Transmission
Communication Function Flowchart
Amended
15.3.5 IrDA Operation
Table 15.12 Bit IrCKS2 to IrCKS0 Settings
φ = 12 MHz or more deleted
16.2.1 I²C Bus Data
Register
TDRE flag: Description amended when TDRE is 1
16.2.4 I²C Bus Mode
Register
Bits 5 to 3: Transfer rate φ = 16 MHz or more deleted
16.2.5 I²C Bus Control
Register
Bits 7: Description amended when ICE is 0
Bits 1: Description amended when IRIC is 1
16.2.6 I²C Bus Status
Register
Bit 0: Description added
"When writing to this bit, ...bit-manipulation instructions."
16.2.7 Serial/Timer Control Bit 3: Description amended
Register
16.3.1 I²C Bus Data Format Figure 16.4 Formatless added
16.3.2 Master Transmit
Operation
Completely amended
16.3.3 Master Receive
Operation
Completely amended
16.3.7 Automatic Switching Description on preconditions amended (formatless
from Formatless Mode to operation)
I²C Bus Format