HD64F2149 Datasheet, PDF (867/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Instruction
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SUBS #1/2/4,ERd R:W NEXT
SUBX #xx:8,Rd R:W NEXT
SUBX Rs,Rd
R:W NEXT
TAS @ERd*⁵
R:W 2nd R:W NEXT R:B:M EA W:B EA
TRAPA Advanced R:W NEXT Internal W:W
W:W
W:W
#x:2
operation, Stack (L) Stack (H) Stack
1 state
(EXR)
R:W:M
VEC
R:W
VEC+2
Internal R:W *⁸
operation,
1 state
XOR.B #xx8,Rd R:W NEXT
XOR.B Rs,Rd
R:W NEXT
XOR.W #xx:16,Rd R:W 2nd R:W NEXT
XOR.W Rs,Rd
R:W NEXT
XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
XOR.L ERs,ERd R:W 2nd R:W NEXT
XORC #xx:8,CCR R:W NEXT
XORC #xx:8,EXR R:W 2nd R:W NEXT
Reset Advanced R:W:M
excep-
VEC
tion
handling
R:W
VEC+2
Internal R:W *⁶
operation,
1 state
Interrupt Advanced R:W *⁷
excep-
tion
handling
Internal W:W
W:W
W:W
operation, Stack (L) Stack (H) Stack
1 state
(EXR)
R:W:M
VEC
R:W
VEC+2
Internal R:W *⁸
operation,
1 state
Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6.
2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented
by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these
bus cycles are not executed.
3. Repeated two times to save or restore two registers, three times for three registers, or
four times for four registers.
4. Start address after return.
5. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
6. Start address of the program.
7. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery
from sleep mode or software standby mode the read operation is replaced by an
internal operation.
8. Start address of the interrupt-handling routine.
9. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
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