HD64F2149 Datasheet, PDF (190/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

6.5 Burst ROM Interface
6.5.1 Overview
With the H8S/2169 or H8S/2149, external space area 0 can be designated as burst ROM space,
and burst ROM interfacing can be performed.
External space can be designated as burst ROM space by means of the BRSTRM bit in BCR.
Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU
instruction fetches only. One or two states can be selected for burst access.
6.5.2 Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordance
with the setting of the AST bit. Also, when the AST bit is set to 1, wait state insertion is possible.
One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in
BCR. Wait states cannot be inserted.
When the BRSTS0 bit in BCR is cleared to 0, burst access of up to 4 words is performed; when
the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figure 6.14 (a) and (b). The timing
shown in figure 6.14 (a) is for the case where the AST and BRSTS1 bits are both set to 1, and that
in figure 6.14 (b) is for the case where both these bits are cleared to 0.
Full access
Burst access
T₁
T₂
T₃
T₁
T₂
T₁
T₂
ø
Address bus
Only lower address changed
AS/IOS (IOSE = 0)
RD
Data bus
Read data
Read data
Read data
Figure 6.14 (a) Example of Burst ROM Access Timing (When AST = BRSTS1 = 1)
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