HD64F2149 Datasheet, PDF (736/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 23.1 CPG Registers
Name
Abbreviation R/W
Standby control register
SBYCR
R/W
Low-power control register LPWRCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
Address*
H'FF84
H'FF85
23.2 Register Descriptions
23.2.1 Standby Control Register (SBYCR)
Bit
7
6
5
4
3
2
1
0
SSBY STS2 STS1 STS0
—
SCK2 SCK1 SCK0
Initial value
0
0
0
0
0
0
0
0
Read/Write ^R/W
R/W
R/W
R/W
—
R/W R/W R/W
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
Only bits 0 to 2 are described here. For a description of the other bits, see section 24.2.1, Standby
Control Register (SBYCR).
SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock
for high-speed mode and medium-speed mode.
When operating the device after a transition to subactive mode or watch mode bits SCK2 to SCK0
should all be cleared to 0.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
Bus master is in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
(Initial value)
702