HD64F2149 Datasheet, PDF (113/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
3.2.3 Bus Control Register (BCR)
Bit
Initial value
Read/Write
7
ICIS1
1
R/W
6
5
4
3
2
ICIS0 BRSTRM BRSTS1 BRSTS0 —
1
0
1
0
1
R/W
R/W
R/W
R/W
R/W
1
IOS1
1
R/W
0
IOS0
1
R/W
BCR is an 8-bit readable/writable register that specifies the external memory space access mode,
and the I/O area range when the AS pin is designated for use as the I/O strobe. For details on bits 7
to 2, see section 6.2.1, Bus Control Register (BCR).
BCR is initialized to H'D7 by a reset and in hardware standby mode.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): These bits specify the addresses for which the
AS/IOS pin output goes low when IOSE = 1.
Bit 1
IOS1
0
BCR
Bit 0
IOS0
0
1
1
0
1
Description
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F03F
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F0FF
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F3FF
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F7FF
(Initial value)
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