HD64F2149 Datasheet, PDF (13/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

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Item
Revision (See Manual for Details)
23.10 X1 and X2 Pins
Added
24.1 Overview
Table 24.1 The Chip's Internal States in Each Mode
HIF: LPC added
I/O: State amended in subsleep mode
24.1.1 Register
Configuration
Table 24.3 Power-Down State Registers
Note 2 added
24.2.2 Low-Power Control Bits 3, 2 to 0 description amended
Register
24.5.1 Module Stop Mode Table 24.4 MSTP Bits and Corresponding On-Chip
Supporting Modules
MSTP2 bit module amended
24.6.3 Setting Occillation Table 24.5 Oscillation Setting Time Settings
Setting Time after Clearing _{φ = 12 MHz or more deleted}
Software Standby Mode
Note amended
25.1 Absolute Maximum
Ratings
Table 25.1 Absolute Maximum Ratings
Value amended
Note added
25.2 DC Characteristics Completely amended
25.3.1 Clock Timing
Table 25.5 Clock Timing
Amendment due to condition change
25.3.2 Control Signal
Timing
Table 25.6 Control Signal Timing
Amendment due to condition change
25.3.3 Bus Timing
Table 25.7 Bus Timing
Amendment due to condition change
25.3.4 Timing of On-Chip Table 25.8 Timing of On-Chip Supporting Modules
Supporting Modules
Amendment due to condition change
Table 25.9 Keyboard Buffer Controller Timing
Amendment due to condition change
Table 25.10 I²C Bus Timing
Amendment due to condition change
Table 25.11 LPC Module Timing
Amendment due to condition change
Figure 25.28 Host Interface(LPC) Timing
LCLK timing amended