HD64F2149 Datasheet, PDF (354/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

11.3.7 Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).
Figure 11.13 shows the timing of this operation.
ø
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 11.13 Setting of Overflow Flag (OVF)
11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to
OCRA is performed. The OCRA write timing is shown in figure 11.14.
ø
FRC
N
N+1
OCRA
N
N+A
OCRAR, F
A
Compare-match
signal
Figure 11.14 OCRA Automatic Addition Timing
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