HD64F2149 Datasheet, PDF (376/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 3
OS3
0
1
Bit 1
OS1
0
1
Bit 2
OS2
0
1
0
1
Bit 0
OS0
0
1
0
1
Description
No change when compare-match B occurs
(Initial value)
0 is output when compare-match B occurs
1 is output when compare-match B occurs
Output is inverted when compare-match B occurs (toggle output)
Description
No change when compare-match A occurs
(Initial value)
0 is output when compare-match A occurs
1 is output when compare-match A occurs
Output is inverted when compare-match A occurs (toggle output)
12.2.6 Serial/Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
IICS IICX1 IICX0 IICE FLSHE —
ICKS1 ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W R/W
R/W R/W R/W
R/W R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), and on-chip flash memory and also selects the TCNT
input clock.
For details on functions not related to the 8-bit timers, see section 3.2.4, Serial/Timer Control
Register (STCR), and the descriptions of the relevant modules. If a module controlled by STCR is
not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4—I²C Control (IICS, IICX1, IICX0, IICE): These bits control the operation of the
I²C bus interface, etc. when the IIC option is included on-chip. See section 3.2.4, Serial/Timer
Control Register (STCR) and section 16, I²C Bus Interface, for details.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls the access of CPU to the
flash memory control registers, the power-down mode control registers, and the supporting
module control registers. See section 3.2.4, Serial/Timer Control Register (STCR).
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