HD64F2149 Datasheet, PDF (851/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SUBS
SUBS #1/2/4,ERd
1
SUBX
SUBX #xx:8,Rd
1
SUBX Rs,Rd
1
TAS
TAS @ERd*³
2
2
TRAPA
TRAPA #x:2 Normal
2
1
2/3 *¹
2
Advanced 2
2
2/3 *¹
2
XOR
XOR.B #xx:8,Rd
1
XOR.B Rs,Rd
1
XOR.W #xx:16,Rd
2
XOR.W Rs,Rd
1
XOR.L #xx:32,ERd
3
XOR.L ERs,ERd
2
XORC
XORC #xx:8,CCR
1
XORC #xx:8,EXR
2
Notes: 1. 2 when EXR is invalid, 3 when valid.
2. When n bytes of data are transferred.
3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
4. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
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