HD64F2149 Datasheet, PDF (595/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

HICR
Bit 0
FGA20E
0
1
P8DDR
Bit 1
P81DDR
0
1
0
1
Description
HIF:XBS fast A20 gate function disabled
HIF:XBS fast A20 gate function disabled
Setting prohibited
HIF:XBS fast A20 gate function enabled
(Initial value)
HICR2 Bit 0—Reserved: Do not set to 1.
18A.2.4 Input Data Register (IDR)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
0
IDR0
—
R
W
IDRn (n = 1 to 4) is an 8-bit read-only register to the slave processor, and an 8-bit write-only
register to the host processor. When CSn (n = 1 to 4) is low, information on the host data bus is
written into IDRn at the rising edge of IOW. The HA0 state is also latched into the C/D bit in
STRn to indicate whether the written information is a command or data.
The initial values of IDR after a reset and in standby mode are undetermined.
18A.2.5 Output Data Register (ODR)
Bit
7
ODR7
Initial value
—
Slave Read/Write R/W
Host Read/Write R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
0
ODR0
—
R/W
R
ODRn (n = 1 to 4) is an 8-bit readable/writable register to the slave processor, and an 8-bit read-
only register to the host processor. The ODRn contents are output on the host data bus when HA0
is low, CSn (n = 1 to 4) is low, and IOR is low.
The initial values of ODR after a reset and in standby mode are undetermined.
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