HD64F2149 Datasheet, PDF (579/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Start
[1] Read KBCRL, and if KBF = 1,
perform processing 1.
Receive state
Read KBCRL
No
KBF = 0?
Yes
Read KBCRH
RXCR3 to RXCR0 ≥
B'1001?
Yes
Disable receive abort
requests
No
[3]
[1]
Processing 1
[2] Read KBCRH, and if the value of
bits RXCR3 to RXCR0 is less than
B'1001, write 0 in KCLKO to abort
reception.
If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, wait
until stop bit reception is
completed, then perform receive
data processing, and proceed to
the next operation.
[3] If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, the
parity bit is being received. With
the PS2 interface, a receive abort
[2]
request following parity bit
reception is disabled. Wait until
KCLKO = 0
stop bit reception is completed,
(receive abort request)
perform receive data processing
and clear the KBF flag, then
proceed to the next operation.
Retransmit
command transmission
(data)?
No
Yes
KBE = 0
(disable KBBR reception
and clear receive counter)
KBE = 0
(disable KBBR reception
and clear receive counter)
Set start bit
(KDO = 0)
KBE = 1
(enable KB operation)
Clear I/O inhibit
(KCLKO = 1)
Clear I/O inhibit
(KCLKO = 1)
Transmit data
To transmit operation
To receive operation
Figure 17.7 Sample Receive Abort Processing Flowchart
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