HD64F2149 Datasheet, PDF (500/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Initialization
[1]
Start transmission/reception
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[1] SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0
to 1 can also be identified by a TXI
interrupt.
[3] Receive error handling:
If a receive error occurs, read the
Read ORER flag in SSR
ORER flag in SSR , and after
performing the appropriate error
handling, clear the ORER flag to 0.
ORER = 1?
Yes
[3]
Transmission/reception cannot be
resumed if the ORER flag is set to
1.
No
Error handling
[4] SCI status check and receive data
read:
Read RDRF flag in SSR
[4]
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
No
RDRF = 1?
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
Note:
Yes
[5]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
<End>
When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to
0, then set both these bits to 1 simultaneously.
Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR and clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit-data-empty
interrupt (TXI) request and data is
written to TDR. Also, the RDRF flag
is cleared automatically when the
DTC is activated by a receive-data-
full interrupt (RXI) request and the
RDR value is read.
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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