HD64F2149 Datasheet, PDF (651/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 18B.8 HIRQ Setting and Clearing Conditions
Host Interrupt
HIRQ1
(independent
from IEDIR)
HIRQ12
(independent
from IEDIR)
Setting Condition
Clearing Condition
Internal CPU writes to ODR1, then reads Internal CPU writes 0 in bit IRQ1E1,
0 from bit IRQ1E1 and writes 1
or host reads ODR1
Internal CPU writes to ODR1, then reads Internal CPU writes 0 in bit IRQ12E1,
0 from bit IRQ12E1 and writes 1
or host reads ODR1
SMI
(IEDIR = 0)
Internal CPU
• writes to ODR2, then reads 0 from bit
SMIE2 and writes 1
• Internal CPU writes 0 in bit SMIE2,
or host reads ODR2
• writes to ODR3, then reads 0 from bit • Internal CPU writes 0 in bit
SMIE3A and writes 1
SMIE3A, or host reads ODR3
• writes to TWR15, then reads 0 from bit • Internal CPU writes 0 in bit
SMIE3B and writes 1
SMIE3B, or host reads TWR15
SMI
(IEDIR = 1)
Internal CPU
• reads 0 from bit SMIE2, then writes 1 • Internal CPU writes 0 in bit SMIE2
• reads 0 from bit SMIE3A, then writes 1 • Internal CPU writes 0 in bit SMIE3A
• reads 0 from bit SMIE3B, then writes 1 • Internal CPU writes 0 in bit SMIE3B
HIRQi
Internal CPU
(i = 6, 9, 10, 11) _{• writes to ODR2, then reads 0 from bit}
(IEDIR = 0)
IRQIE2 and writes 1
• Internal CPU writes 0 in bit IRQIE2,
or host reads ODR2
• writes to ODR3, then reads 0 from bit • Internal CPU writes 0 in bit IRQIE3,
IRQIE3 and writes 1
or host reads ODR3
HIRQi
(i = 6, 9, 10, 11)
(IEDIR = 1)
Internal CPU
• reads 0 from bit IRQIE2, then writes 1
• reads 0 from bit IRQIE3, then writes 1
• Internal CPU writes 0 in bit IRQIE2
• Internal CPU writes 0 in bit IRQIE3
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