HD64F2149 Datasheet, PDF (704/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 1
ESU
0
1
Description
Erase setup cleared
Erase setup
[Setting condition]
When SWE = 1
(Initial value)
Bit 0—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before
setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 0
PSU
0
1
Description
Program setup cleared
Program setup
[Setting condition]
When SWE = 1
(Initial value)
22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
Bit
7
6
5
4
3
2
1
0
EBR1
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
—*²
—*²
—*²
—*²
—*²
—*²
—*²
—*²
Bit
7
6
5
4
3
2
1
0
EBR2
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W*¹ R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: 1. In normal mode, these bits cannot be modified and are always read as 0.
2. This bit must not be set to 1.
EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 7 to 0
in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized to H'00 by a reset, in
hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch
mode, and when the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding
block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 (more than one bit
cannot be set). When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
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