HD64F2149 Datasheet, PDF (426/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

14.1.2 Block Diagram
Figures 14.1 (a) and (b) show block diagrams of WDT0 and WDT1.
WOVI0
(interrupt request
signal)
Internal NMI
interrupt request
signal^*2
RESO signal^*1
Internal reset
signal^*1
Interrupt
control Overflow
Reset
control
Clock
Clock
select
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Internal clock
source
TCNT
TCSR
Module bus
Bus
interface
WDT0
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
Notes: 1. RESO pin output goes low when the internal reset signal is generated by overflow of TCNT
in either WDT0 or WDT1. The reset of the WDT that overflowed first takes precedence over
the internal reset signal.
2. The internal NMI interrupt request signal can be output independently by either WDT0 or
WDT1. The interrupt controller does not distinguish between NMI interrupt requests from
WDT0 and WDT1.
Figure 14.1 (a) Block Diagram of WDT0
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