HD64F2149 Datasheet, PDF (143/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.2.8 Address Break Control Register (ABRKCR)
Bit
7
6
5
4
3
2
1
0
CMF
—
—
—
—
—
—
BIE
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
—
—
—
—
—
—
R/W
ABRKCR is an 8-bit readable/writable register that performs address break control.
ABRKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Condition Match Flag (CMF): This is the address break source flag, used to indicate that
the address set by BAR has been prefetched. When the CMF flag and BIE flag are both set to 1, an
address break is requested.
Bit 7
CMF
0
1
Description
[Clearing condition]
When address break interrupt exception handling is executed
[Setting condition]
When address set by BARA to BARC is prefetched while BIE = 1
(Initial value)
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Break Interrupt Enable (BIE): Selects address break enabling or disabling.
Bit 0
BIE
0
1
Description
Address break disabled
Address break enabled
(Initial value)
109