HD64F2149 Datasheet, PDF (8/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

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Item
Revision (See Manual for Details)
4.1.3 Exception Source and Table 4.2 Exception Vector Table
Vector Table
Internal interrupt address amended
5.1.2 Block Diagram
Figure 5.1 Block Diagram of Interrupt Controller
Names of Internal interrupt request amended
5.2.2 Interrupt Control
Registers A to C
Description amended (address break)
5.2.5 IRQ Status Register Bits 7 to 0: Note added
5.2.6 Keyboard Matrix
interrupt Mask Register
Description and note amended
5.3.1 External Interrupt Description on IRQ6 pin added
5.3.3 Interrupt Sources,
Vector Addresses, and
Interrupt Priorities
Interrupt Source name amended (address break (PC
break))
5.5.1 Interrupt Control
Modes and Interrupt
Operation
Description amended (address break)
Table 5.6 Interrupt Selected in Each Interrupt Control
Mode
Description amended (address break)
5.5.2 Interrupt Control
Mode 0
Description amended (address break)
Figure 5.8 Flowchart of Procedure Up to Interrupt
Acceptance in Interrupt Control Mode 0
Interrupt name amended (IBFI3)
5.5.3 Interrupt Control
Mode 1
Description amended (address break)
Figure 5.10 Flowchart of Procedure Up to Interrupt
Acceptance in Interrupt Control Mode 1
Interrupt name amended (IBFI3)
5.5.5 Interrupt Response
Times
Table 5.8 Interrupt Response Times
Number of wait states until execution instruction ends
amended
6.2.2.Wait State Control
Register
Bits 7 and 6 description amended
6.3.4 I/O Select Signal
Table 6.4 IOS Signal Output Range Settings
Address amended when IOS1 and IOS0 are 1,
respectively
6.4.5 Wait Control
Figure 6.13 Example of Wait State Insertion Timing
HWR, LWR timing amended