HD64F2149 Datasheet, PDF (742/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

23.4 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (ø).
23.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32
clocks.
23.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed
clocks (ø/2, ø/4, ø/8, ø/16, or ø/32) to be supplied to the bus master, according to the settings of
bits SCK2 to SCK0 in SBYCR.
23.7 Subclock Input Circuit
The subclock input circuit controls the subclock input from the EXCL pin.
Inputting the Subclock: When a subclock is used, a 32.768 kHz external clock should be input
from the EXCL pin. In this case, clear bit P96DDR to 0 in P9DDR and set bit EXCLE to 1 in
LPWRCR.
The subclock input conditions are shown in table 23.6 and figure 23.8.
Table 23.6 Subclock Input Conditions
Item
Symbol Min
Subclock input low pulse t_EXCLL
—
width
Subclock input high pulse t_EXCLH
—
width
Subclock input rise time t_EXCLr
—
Subclock input fall time t_EXCLf
—
V_CC = 2.7 to 3.6 V
Typ
Max
15.26 —
15.26 —
—
10
—
10
Unit
µs
µs
ns
ns
Test Conditions
Figure 23.8
708