HD64F2149 Datasheet, PDF (572/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

17.2.3 Keyboard Data Buffer Register (KBBR)
Bit
7
6
5
4
3
2
1
0
KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
KBBR is a read-only register that stores receive data. Its value is valid only when KBF = 1.
KBBR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode, and when KBIOE is cleared to 0.
17.2.4 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
7654321076543210
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable register, performs module stop mode control.
When the MSTP2 bit is set to 1, the keyboard buffer controller halts and enters module stop mode.
See section 24.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 2—Module Stop (MSTP2): Specifies keyboard buffer controller module stop
mode.
MSTPCRL
Bit 2
MSTP2
0
1
Description
Keyboard buffer controller module stop mode is cleared
Keyboard buffer controller module stop mode is set
(Initial value)
538