HD64F2149 Datasheet, PDF (236/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

8.3.2 Register Configuration
Table 8.4 shows the port 2 register configuration.
Table 8.4 Port 2 Registers
Name
Abbreviation R/W
Port 2 data direction register P2DDR
W
Port 2 data register
P2DR
R/W
Port 2 MOS pull-up control
P2PCR
R/W
register
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
H'00
Address*
H'FFB1
H'FFB3
H'FFAD
Port 2 Data Direction Register (P2DDR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2. P2DDR cannot be read; if it is, an undefined value will be returned.
P2DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. The address output pins maintain their output state in a transition to
software standby mode.
• Mode 1
The corresponding port 2 pins are address outputs, regardless of the P2DDR setting.
In hardware standby mode, the address outputs go to the high-impedance state.
• Modes 2 and 3 (EXPE = 1)
The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set
to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output
ports by setting the IOSE bit to 1.
P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting,
but to ensure normal access to external space, P27 should not be set as an on-chip supporting
module output pin when port 2 pins are used as address output pins.
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