HD64F2149 Datasheet, PDF (375/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

TCSR1
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
TCSRX
Bit 4—Input Capture Flag (ICF): Status flag that indicates detection of a rising edge followed
by a falling edge in the external reset signal after the ICST bit in TCONRI has been set to 1.
Bit 4
ICF
0
1
Description
[Clearing condition]
(Initial value)
Read ICF when ICF = 1, then write 0 in ICF
[Setting condition]
When a rising edge followed by a falling edge is detected in the external reset signal
after the ICST bit in TCONRI has been set to 1
TCSRY
Bit 4—Input Capture Interrupt Enable (ICIE): Selects enabling or disabling of the interrupt
request by ICF (ICIX) when the ICF bit in TCSRX is set to 1.
Bit 4
ICIE
0
1
Description
Interrupt request by ICF (ICIX) is disabled
Interrupt request by ICF (ICIX) is enabled
(Initial value)
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is
to be changed by a compare-match of TCOR and TCNT.
OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the
effect of compare-match A on the output level, and both of them can be controlled independently.
Note, however, that priorities are set such that: trigger output > 1 output > 0 output. If compare-
matches occur simultaneously, the output changes according to the compare-match with the higher
priority.
Timer output is disabled when bits OS3 to OS0 are all 0.
After a reset, the timer output is 0 until the first compare-match occurs.
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