HD64F2149 Datasheet, PDF (343/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 1
OVF
0
1
Description
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
[Setting condition]
When FRC changes from H'FFFF to H'0000
(Initial value)
Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at compare-
match A (when the FRC and OCRA values match).
Bit 0
CCLRA
0
1
Description
FRC clearing is disabled
FRC is cleared at compare-match A
(Initial value)
11.2.8 Timer Control Register (TCR)
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
3
2
IEDGD BUFEA BUFEB
0
0
0
R/W R/W R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).
Bit 7
IEDGA
0
1
Description
Capture on the falling edge of FTIA
Capture on the rising edge of FTIA
(Initial value)
Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B
signal (FTIB).
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