HD64F2149 Datasheet, PDF (402/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bits 3 to 0—Input Synchronization Signal Inversion (HFINV, VFINV, HIINV, VIINV):
These bits select inversion of the input phase of the spare horizontal synchronization signal
(HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal
synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the
vertical synchronization signal (VSYNCI).
Bit 3
HFINV
0
1
Description
The HFBACKI pin state is used directly as the HFBACKI input
The HFBACKI pin state is inverted before use as the HFBACKI input
(Initial value)
Bit 2
VFINV
0
1
Description
The VFBACKI pin state is used directly as the VFBACKI input
The VFBACKI pin state is inverted before use as the VFBACKI input
(Initial value)
Bit 1
HIINV
0
1
Description
The HSYNCI and CSYNCI pin states are used directly as the HSYNCI
and CSYNCI inputs
(Initial value)
The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and
CSYNCI inputs
Bit 0
VIINV
0
1
Description
The VSYNCI pin state is used directly as the VSYNCI input
The VSYNCI pin state is inverted before use as the VSYNCI input
(Initial value)
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