HD64F2149 Datasheet, PDF (211/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Register information
start address
Chain transfer
Lower address
0
1
2
3
MRA
SAR
MRB
DAR
CRA
CRB
MRA
SAR
MRB
DAR
CRA
CRB
4 bytes
Register information
Register information
for 2nd transfer
in chain transfer
Figure 7.5 Location of DTC Register Information in Address Space
7.3.5 Normal Mode
In normal mode, one operation transfers one byte or one word of data.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt can be requested.
Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in
normal mode.
Table 7.5 Register Information in Normal Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register A
DTC transfer count register B
Abbreviation
SAR
DAR
CRA
CRB
Function
Transfer source address
Transfer destination address
Transfer count
Not used
177