HD64F2149 Datasheet, PDF (561/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 16.8 I²C Bus Timing (with Maximum Influence of t_Sr/t_Sf)
Item
t_cyc
Indication
Time Indication (at Maximum Transfer Rate) [ns]
t_Sr/t_Sf
Influence
(Max.)
I²C Bus
Specification ø =
(Min.)
5 MHz
ø= ø=
8 MHz 10 MHz
t _SCLHO
0.5t_SCLO
(–t_Sr)
Standard mode –1000
High-speed mode –300
4000
600
4000 4000 4000
950 950 950
t _SCLLO
t _BUFO
t _STAHO
0.5t_SCLO
(–t_Sf )
Standard mode –250
High-speed mode –250
0.5t_SCLO – Standard mode –1000
1t_cyc ( –t_Sr ) _{High-speed mode –300}
0.5t_SCLO – Standard mode –250
1t_cyc (–t_Sf ) _{High-speed mode –250}
4700
1300
4700
1300
4000
600
4750 4750 4750
1000*¹ 1000*¹ 1000*¹
3800*¹ 3875*¹ 3900*¹
750*¹ 825*¹ 850*¹
4550 4625 4650
800 875 900
t _STASO
1t _SCLO
(–t_Sr )
Standard mode –1000
High-speed mode –300
4700
600
9000 9000 9000
2200 2200 2200
t _STOSO
t _SDASO
(master)
t _SDASO
(slave)
0.5t_SCLO +
2t_cyc (–t_Sr )
1t
*³
SCLLO
–
3t_cyc (–t_Sr )
1t_SCLL*³ –
12t _cyc * ²
(–t_Sr )
Standard mode –1000
High-speed mode –300
Standard mode –1000
High-speed mode –300
Standard mode –1000
High-speed mode –300
4000
600
250
100
250
100
4400 4250 4200
1350 1200 1150
3100 3325 3400
400 625 700
1300 2200 2500
–1400*¹ –500*¹ –200*¹
t _SDAHO
3t _cyc
Standard mode 0
0
High-speed mode 0
0
600 375 300
600 375 300
Notes: The maximum operating frequency for the H8S/2169 and H8S/2149 is 10 MHz.
1. Does not meet the I²C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I²C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t_SCLL –
6t_cyc).
3. Calculated using the I²C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).
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