HD64F2149 Datasheet, PDF (310/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

9.2.2 PWM Data Registers (PWDR0 to PWDR15)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each PWDR is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to
be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1
ratio in the conversion period. The upper 4 bits specify the duty cycle of the basic pulse as 0/16 to
15/16 with a resolution of 1/16. The lower 4 bits specify how many extra pulses are to be added
within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256
is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output
should be used.
PWDR is initialized to H'00 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)
PWDPRA
Bit
Initial value
Read/Write
7
OS7
0
R/W
6
OS6
0
R/W
5
OS5
0
R/W
4
OS4
0
R/W
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
PWDPRB
Bit
Initial value
Read/Write
7
OS15
0
R/W
6
OS14
0
R/W
5
OS13
0
R/W
4
OS12
0
R/W
3
OS11
0
R/W
2
OS10
0
R/W
1
OS9
0
R/W
0
OS8
0
R/W
Each PWDPR is an 8-bit readable/writable register that controls the polarity of the PWM output.
Bits OS0 to OS15 correspond to outputs PW0 to PW15.
PWDPR is initialized to H'00 by a reset and in hardware standby mode.
276