HD64F2149 Datasheet, PDF (390/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.6 Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer module.
12.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed. Figure 12.13 shows this
operation.
TCNT write cycle by CPU
T₁
T₂
ø
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 12.13 Contention between TCNT Write and Clear
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